
20
INDUSTRIALTEMPERATURERANGE
IDT5T9890
EEPROM PROGRAMMABLE 2.5V PROGRAMMABLE SKEW PLL CLOCK DRIVER
AC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Alloutputsatthedifferentinterfacelevels
Symbol
Parameter
Min.
Typ.
Max
Unit
FNOM
VCO Frequency Range
see JTAG/I2C Serial Configurations: VCO Frequency Range table
tRPW
Reference Clock Pulse Width HIGH or LOW
1
—
ns
tFPW
Feedback Input Pulse Width HIGH or LOW
1
—
ns
tSK(B)
Output Matched Pair Skew(1,2,4)
—
200
ps
tSK(O)
Output Skew (Rise-Rise, Fall-Fall, Nominal)(1,3)
—
250
ps
tSK1(
ω)
MultipleFrequencySkew(Rise-Rise,Fall-Fall,Nominal-Divided,Divided-Divided)(1,3,4)
—
500
ps
tSK2(
ω)
MultipleFrequencySkew(Rise-Fall,Nominal-Divided,Divided-Divided)(1,3,4)
—
500
ps
tSK1(INV)
InvertingSkew(Nominal-Inverted)(1,3)
——
500
ps
tSK2(INV)
InvertingSkew(Rise-Rise,Fall-Fall,Rise-Fall,Inverted-Divided)(1,3,4)
—
500
ps
tSK(PR)
Process Skew(1,3.5)
——
400
ps
t(
φ)
REF Input to FB Static Phase Offset(6)
-200
—
200
ps
tODCV
Output Duty Cycle Variation from 50%(7)
HSTL / eHSTL / 1.8V LVTTL
-475
—
475
ps
2.5VLVTTL
-375
—
375
tORISE
OutputRiseTime(8)
HSTL / eHSTL / 1.8V LVTTL
—
1.2
ns
2.5VLVTTL
—
1
tOFALL
OutputFallTime(8)
HSTL / eHSTL / 1.8V LVTTL
—
1.2
ns
2.5VLVTTL
—
1
tL
Power-up PLL Lock Time(9)
——
4
ms
tL(
ω)
PLLLockTimeAfterInputFrequencyChange(9)
——
1
ms
tL(REFSEL1)
PLL Lock Time After Change in REF_SEL (9,11)
—
100
s
tL(REFSEL2)
PLL Lock Time After Change in REF_SEL (REF1 and REF0are different frequency)(9)
——
1
ms
tL(PD)
PLL Lock Time After Asserting PD Pin(9)
——
1
ms
tJIT(CC)
Cycle-to-CycleOutputJitter(peak-to-peak)(10)
—
—
100
ps
tJIT(PER)
PeriodJitter(peak-to-peak)(10)
——
150
ps
tJIT(HP)
Half Period Jitter (peak-to-peak, QFB/QFB only)(10,12)
—
200
ps
tJIT(DUTY)
DutyCycleJitter(peak-to-peak)(10)
——
150
ps
VOX
HSTLandeHSTLDifferentialTrueandComplementaryOutputCrossingVoltageLevel
VDDQN/2 - 150 VDDQN/2 VDDQN/2 + 150 mV
QFB/QFB only(12)
NOTES:
1. Skew is the time between the earliest and latest output transition among all outputs when all outputs are loaded with the specified load.
2. tSK(B) is the skew between a pair of outputs (nQ0 and nQ1) when all outputs are selected as the same class.
3. The measurement is made at VDDQN/2.
4. There are three classes of outputs: nominal (multiple of tU), inverted, and divided (divide-by-2 or divide-by-4 mode).
5. tSK(PR) is the output to corresponding output skew between any two devices operating under the same conditions (VDD and VDDQN, ambient temperature, air flow, etc.).
6. t(
φ) is measured with REF and FB the same type of input, the same rise and fall times. For 1.8V / 2.5V LVTTL input and output, the measurement is taken from VTHI on REF
to VTHI on FB. For HSTL / eHSTL input and output, the measurement is taken from the crosspoint of REF/REF to the crosspoint of FB/FB. All outputs are set to 0tU, FB input
divider set to divide-by-one, and Bit 60 = 1.
7. tODCV is measured with all outputs selected for 0tU.
8. Output rise and fall times are measured between 20% to 80% of the actual output voltage swing.
9. tL, tL(
ω), tL(REFSEL1), tL(REFSEL2), and tL(PD) are the times that are required before the synchronization is achieved. These specifications are valid only after VDD/VDDQN is stable and
within the normal operating limits. These parameters are measured from the application of a new signal at REF or FB, or after PD is (re)asserted until t(
φ) is within specified
limits.
10. The jitter parameters are measured with all outputs selected for 0tU, FB input divider is set to divide-by-one, and Bit 60 = 1.
11. Both REF inputs must be the same frequency, but up to ±180° out of phase.
12. For HSTL/eHSTL outputs only.